1. Field of the Invention
This invention relates to the arrangement and structure of the input/output cells in a semiconductor device, particularly, in a semiconductor integrated circuit device.
2. Description of the Prior Art
FIG. 7 is a schematic view of a conventional semiconductor integrated circuit device. This semiconductor integrated circuit device has an internal logic circuit area 31 and two input/output cell groups 10 and 20 on a semiconductor substrate (not shown). The internal logic circuit area 31 is designed so as to have an arbitrary function. Signal wiring is provided between the two input/output cell groups 10 and 20 and the internal logic circuit area 31 or between the input/output cells of the input/output cell group 10 and the input/output cells of the input/output cell group 20 so that signal transfer is performed between the internal logic circuit area 31 and an external device (not shown) through the two input/output cell groups 10 and 20.
The two input/output cell groups 10 and 20 comprise a plurality of input/output cells 11 and 21, respectively. The input/output cells 11 and 21 are each arranged in a square loop so that the square internal logic circuit area 31 is surrounded by two loops.
The inside input/output cell group 10 comprises a multiplicity of input/output cells 11 and four corner cells 11A comprising blank cells. The cells are arranged in a square loop on the semiconductor substrate so as to surround the square internal logic circuit area 31 situated substantially in the center of the semiconductor substrate. The outside input/output cell group 20 comprises a multiplicity of input/output cells 21 and four corner cells 21A comprising blank cells. The cells are arranged in a square loop so as to surround the inside input/output cell group 10.
A space 41 for providing wiring between the internal logic circuit area 31 and the outside input/output cell group 20 is provided between the inside input/output cell group 10 and the outside input/output cell group 20. A space for providing wiring is also provided between the internal logic circuit area 31 and the inside input/output cell group 10.
The input/output cells 11 of the inside input/output cell group 10 each have a high potential side guard band 12, a low potential side guard band 13 and a bonding pad 14. The high potential side guard band 12 is disposed on the side closer to the internal logic circuit area 31. The low potential side guard band 13 is disposed outside the high potential side guard band 12. The bonding pad 14 is disposed outside the low potential side guard band 13. The high potential side guard band 12 is supplied with a high potential supply voltage V.sub.DD, whereas the low potential side guard band 13 is supplied with a low potential supply voltage V.sub.SS. The bonding pad 14 is connected to an external device to perform signal transfer with the external device.
The input/output cells 21 of the outside input/output cell group 20 each have a high potential side guard band 22, a low potential side guard band 23 and a bonding pad 24. The high potential side guard band 22 is disposed on the side closer to the internal logic circuit area 31. The low potential side guard band 23 is disposed outside the high potential side guard band 22. The bonding pad 24 is disposed outside the low potential side guard band 23. The high potential side guard band 22 is supplied with the high potential supply voltage V.sub.DD, whereas the low potential side guard band 23 is supplied with the low potential supply voltage V.sub.SS. The bonding pad 24 is connected to an external device to perform signal transfer with the external device.
The corner cells 11A have no guard bands. The corner cells 21A each have a low potential side guard band 23A electrically connected to the low potential side guard band 23.
On the semiconductor substrate, wiring 51 as, for example, signal lines is provided. The wiring 51 made of a metal such as aluminum or copper electrically connects the internal logic circuit area 31 and the outside input/output cells 21.
The input/output cells 11 and 21 are incorporated in the semiconductor integrated circuit device in order to perform signal transfer with an external device. The input/output cells 11 and 21 include not only input/output elements but also elements for protecting the semiconductor integrated circuit device from externally applied high voltages such as noises and bonding pads 14 and 24 for performing signal transfer with an external device.
FIG. 8 shows an example of an equivalent circuit of the input/output cells 11. The input/output cells 11 each comprise, as shown in FIG. 8, a P-channel transistor 201 which is a P-channel input element, an N-channel transistor 202 which is an N-channel input element, a P-channel transistor 203 which is a P-channel output element, an N-channel transistor 204 which is an N-channel output element, a P-channel transistor 205 which is a P-channel protecting element, and an N-channel transistor 206 which is an N-channel protecting element.
The source of the P-channel transistor 201 is connected to the high potential supply voltage V.sub.DD. The source of the N-channel transistor 202 is connected to the low potential supply voltage V.sub.SS. The gate of the P-channel transistor 201 and the gate of the N-channel transistor 202 are joined and connected to the bonding pad 14. The drain of the P-channel transistor 201 and the drain of the N-channel transistor 202 are joined and connected to the internal logic circuit area 31.
The source of the P-channel transistor 203 is connected to the high potential supply voltage V.sub.DD. The source of the N-channel transistor 204 is connected to the low potential supply voltage V.sub.SS. The drain of the P-channel transistor 203 and the drain of the N-channel transistor 204 are joined and connected to the bonding pad 14. The gate of the P-channel transistor 203 and the gate of the N-channel transistor 204 are joined and connected to the internal logic circuit area 31.
The source and the gate of the P-channel transistor 205 are joined and connected to the high potential supply voltage V.sub.DD. The source and the gate of the N-channel transistor 206 are joined and connected to the low potential supply voltage V.sub.SS. The drain of the P-channel transistor 205 and the drain of the N-channel transistor 206 are joined and connected to the bonding pad 14.
The input/output cells 21 have the same circuit structure as the input/output cells 11.
Because of this circuit structure, the guard bands 12, 13, 22 and 23 are normally formed in the input/output cells 11 and 21, and by the guard bands 12, 13, 22 and 23, the input/output cells 11 and 21 are protected. By arranging the input/output cells 11 and 21 in loops, the guard bands 12, 13, 22 and 23 form rings surrounding the internal logical circuit area 31, whereby the internal logic circuit area 31 is protected. The rings formed by the guard bands 12, 13, 22 and 23 are called guard rings.
The elements for protecting the semiconductor integrated circuit device from externally applied high voltages are provided for the following purpose: Since external signals are directly supplied to the semiconductor integrated circuit device through the bonding pads 14 and 24, in order to protect the semiconductor integrated circuit device, an element is provided for causing an overcurrent to flow toward the high potential side when a high voltage is applied. In this case, toward the high potential side, the overcurrent is caused to flow from the drain of the P-channel transistor 205 which is a protecting element. Toward the low potential side, the overcurrent is caused to flow from the drain of the N-channel transistor 206 which is a protecting element.
By surrounding the portions where the overcurrent flows, for example, by the square-loop-shaped guard bands 12, 13, 22 and 23 and absorbing a trigger current which is a factor that causes latch up by the guard bands 12, 13, 22 and 23, the generation of latchup in the input/output cells 11 and 21 are prevented, whereby the input/output cells 11 and 21 are protected.
Further, by arranging the input/output cells 11 and 12 in loops so that the guard bands 12, 13, 22 and 23 surround the internal logic circuit area 31, the trigger current caused by noise or the like and flowing from the bonding pads 14 and 24 into the internal logic circuit area 31 to cause latchup is absorbed by the rings of the guard bands 12, 13, 22 and 23 to thereby prevent the generation of latchup in the internal logic circuit area 31, whereby the internal logic circuit area 31 is protected.
According to the conventional method of arranging the input/output cells in a semiconductor integrated circuit device, the wiring 51 connecting the internal logic circuit area 31 and the outside input/output cells 21 passes above the inside input/output cells 11. Describing concretely, polysilicon layers and aluminum wiring layers for forming transistors are present in the input/output cells 11. Therefore, the metal line of another layer that is not used in the input/output cells 11 is passed above the input/output cells 11. For example, when the input/output cells 11 use the aluminum wirings of the first and the second layers, the aluminum wiring of the third layer is used as the wiring 51. Moreover, it is necessary to form the bonding pad 14 on the layer above the layer whose wiring is used as the wiring 51.
FIG. 9 is a schematic view showing the layout of a typical input/output cell. As shown in FIG. 9, in the layout of the input/output cell, the bonding pad 14 for performing signal transfer with an external device is disposed in the lowermost part of the input/output cell 11, that is, the part situated outside when the input/output cells 11 are arranged in a loop, whereas the square-loop-shaped high potential side guard band 12 and the square-loop-shaped low potential side guard band 13 are formed above the bonding pad 14, that is, in a part situated inside when the input/output cells 11 are arranged in a loop. The high potential side guard band 12 is supplied with the high potential supply voltage V.sub.DD. The low potential side guard band 13 is supplied with the low potential supply voltage V.sub.SS.
In order that the trigger current flowing from the bonding pads 14 and 24 into the internal logic circuit area 31 to cause latchup is effectively absorbed, the bonding pads 14 and 24 are disposed on the outermost side of the input/output cells 10 and 20.
The high potential side guard bands 12 and the low potential side guard bands 13 are formed in square loops around a P-channel element and protecting element formed area 12A and an N-channel element and protecting element formed area 13A, respectively. This applies to the input/output cells 21.
While the guard bands 12 and 13 are each drawn as one line in FIG. 7, this is for simplification of the figure, and in actuality, the guard bands 12 and 13 each have a square loop shape as mentioned above. This applies to embodiments described later.
In fabricating a semiconductor integrated circuit device, for example, the input/output cells 11 are arranged in a square loop around the logical circuit area 31 as shown in FIG. 7, whereby the high potential side guard bands 12 and the low potential side guard bands 13 are electrically connected to form guard rings.
An example of a cross-sectional structure of the input/output cells 11 will be described with reference to FIG. 10. In FIG. 10, in the input/output cell 11, an N.sup.+ -type well 62 and a P.sup.+ -type well 63 are formed in a P-type semiconductor substrate 61.
In a peripheral part of the N.sup.+ -type well 62, a diffusion layer 64 for the high potential side guard band is formed in a square loop. On the diffusion layer 64, a metal layer 66 such as an aluminum layer for the high potential side guard band is formed in a square loop. The metal layer 66 is connected to the diffusion layer 64 by a contact. The diffusion layer 64 and the metal layer 66 correspond to the high potential side guard band 12 of FIG. 9.
In a peripheral part of the P.sup.+ -type well 63, a diffusion layer 65 for the low potential side guard band is formed in a square loop. On the diffusion layer 65, a metal layer 67 such as an aluminum layer for the low potential side guard band is formed in a square loop. The metal layer 67 is connected to the diffusion layer 65 by a contact. The diffusion layer 65 and the metal layer 67 correspond to the low potential side guard band 13 of FIG. 9.
A P-channel input/output element and protecting element formed area 68 surrounded by the high potential side guard band comprising the diffusion layer 64 and the metal layer 66 corresponds to the P-channel input/output element and protecting element formed area 12A. An N-channel input/output element and protecting element formed area 69 surrounded by the low potential side guard band comprising the diffusion layer 65 and the metal layer 67 corresponds to the N-channel input/output element and protecting element formed area 13A.
The P-channel input/output element and protecting element formed area 68 and the P-channel input/output element and protecting element formed area 69 are protected by a protecting film (SOG (spin on glass)) 70 formed on the surface of the P-type semiconductor substrate 61.
In FIG. 10, the P-channel elements and the N-channel elements formed in the N.sup.+ -type well 62 and the P.sup.+ -type well 63 (the P-channel transistors 201, 203 and 205 and the N-channel elements 202, 204 and 206 of FIG. 8) are not illustrated.
The guard bands basically have the two-layer structure of a diffusion layer and a metal layer as described above.
The difference between power supply wiring and the guard bands will be described. The power supply wiring, which is basically an aluminum layer, is a line connecting with the power supply line to which the power supply wiring is to be connected. On the contrary, the guard bands, although connecting with the power supply line, connect with a well potential (substrate potential) directly.
Next, the function of the guard bands will be described with reference to FIG. 11. FIG. 11 is a cross-sectional view of a part of the input/output cell. Parasitically formed elements are represented by circuit symbols. In FIG. 11, in the input/output cell, an N.sup.+ -type well 82 is formed in a P-type semiconductor substrate 81. A P.sup.+ -type diffusion layer 83 is formed in the N.sup.+ -type well 82. The P.sup.+ -type diffusion layer 83 serves as the drain of a P-channel MOS transistor as a P-channel output element. Moreover, a P.sup.+ -type diffusion layer 84 is formed in the N.sup.+ -type well 82. The P.sup.+ -type diffusion layer 84 serves as the source of the above-mentioned P-channel MOS transistor. Further, a polysilicon layer 85 serving as the gate of the P-channel MOS transistor is formed above the N.sup.+ -type well 82 in a position between the P.sup.+ -type diffusion layers 83 and 84. Moreover, an N.sup.+ -type diffusion layer 86 is formed in the N.sup.+ -type well 82. The N.sup.+ -type diffusion layer 86 is used for contact with the N.sup.+ -type well 82. An N.sup.+ -type diffusion layer 98 formed in the N.sup.+ -type well 82 serves as the high potential side guard band, is supplied with the high potential supply voltage V.sub.DD and corresponds to the diffusion layer 64 of FIG. 10. A P.sup.+ -type diffusion layer 99 formed in the P-type semiconductor substrate 81 serves as the low potential side guard band, is supplied with the low potential supply voltage V.sub.SS and corresponds to the diffusion layer 65 of FIG. 10.
On the other hand, a diffusion layer 87 is formed in the P-type semiconductor substrate 81. The N.sup.+ -type diffusion layer 87 serves as the drain of an N-channel MOS transistor as an N-channel output element. An N.sup.+ -type diffusion layer 88 is formed in the P-type semiconductor substrate 81. The N.sup.+ -type diffusion layer 88 serves as the source of the above-mentioned N-channel MOS transistor. Further, a polysilicon layer 89 serving as the gate of the N-channel MOS transistor is formed above the P-type semiconductor substrate 81 in a position between the N.sup.+ -type diffusion layers 87 and 88. Moreover, a P.sup.+ -type diffusion layer 90 is formed in the P-type semiconductor substrate 81. The P.sup.+ -type diffusion layer 90 is used for contact with the P-type semiconductor substrate 81.
The N.sup.+ -type well 82 corresponds to the N.sup.+ -type well 62 of FIG. 10. A P.sup.+ -type well corresponding to the P.sup.+ -type well 63 of FIG. 10 is not shown. The P.sup.+ -type well is not always necessary.
An output terminal 91 for obtaining an output V.sub.OUT is connected to the P.sup.+ -type diffusion layer 83 and the N.sup.+ -type diffusion slayer 87. A high potential power supply wiring 92 is connected to the P.sup.+ -type diffusion layer 84 and the N.sup.+ -type diffusion layer 86, and is supplied with the high potential supply voltage V.sub.DD. A low potential power supply wiring 93 is connected to the N.sup.+ -type diffusion layer 88 and the P.sup.+ -type diffusion layer 90, and is supplied with the low potential supply voltage V.sub.SS.
In the input/output cell of the above-described structure, for example, PNP-type parasitic transistors 94 and 95, NPN-type parasitic transistors 96 and 97, and parasitic resistors r.sub.1, r.sub.2, r.sub.3 and r.sub.4 are present.
In the above-described structure, for example, when a high voltage is applied to the output terminal 91 by the high potential supply voltage V.sub.DD, a trigger current is supplied as the emitter current from the output terminal 91 to the parasitic transistor 94 in a forward direction. Then, the collector current of the parasitic transistor 94 flows to the P-type semiconductor substrate 81. This causes latchup.
On the contrary, the trigger current can be absorbed by disposing the guard band in the vicinity of the portion where the trigger current is generated, whereby the amount of latchup resistance is improved.
FIG. 12 shows the parasitic transistors 95 and 97 and the parasitic resistors r.sub.1, r.sub.2, r.sub.3 and r.sub.4 in the CMOS circuit of FIG. 11. The transistors 95 and 97 and the resistors r.sub.1 to r.sub.4 form a thyristor structure, and latchup occurs in this portion. In FIG. 12, by reducing the parasitic resistors (base resistors) r.sub.1 and r.sub.4 by applying the high potential supply voltage V.sub.DD to the base of the parasitic transistor 95 and applying the low potential supply voltage V.sub.SS to the base of the parasitic transistor 96 as shown by the broken lines by use of the guard band, the latchup can be restrained.
For semiconductor integrated circuit devices, the technology to increase the speed, the degree of integration and the number of pins has advanced year by year. In the advancement of the technology, as the degree of integration and the number of pins have increased, the influence of the chip size because of the size of the input/output circuit has become a problem. This is because, as described above, the input/output circuit cannot be increased in degree of integration as much as the internal element since the circuit for protecting the semiconductor integrated circuit device from externally applied high voltages (noises, etc.) is incorporated in the input/output circuit.
For this reason, in a semiconductor integrated circuit device having an increased number of pins, a multiplicity of input/output circuits are disposed, so that the chip size depends on the input/output circuits.
Therefore, in order to reduce the chip size, the input/output cell groups are arranged in a plurality of loops as shown in the conventional example. However, when the input/output cell groups are arranged in a plurality of loops, since there is an input/output cell group inside, it is difficult to connect the outside input/output cell group and the internal logic circuit area.